PIC16F737-I/SP【PDF 195/231 页】IC PIC MCU FLASH 4KX14 28DIP

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Sheet目录3841

191页 192页 193页 194页 [195页]196页 197页 198页 199页

2004 Microchip Technology Inc.

DS30498C-page 27

PIC16F7X7

2.2.2.7

PIR2 Register

The PIR2 register contains the flag bits for the CCP2

interrupt.

REGISTER 2-7:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0

U-0

R/W-0

U-0

R/W-0

OSFIF

CMIF

LVDIF

—BCLIF

—

CCP3IF

CCP2IF

bit 7

bit 0

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

= System oscillator failed, clock input has changed to INTRC (must be cleared in software)

= System clock operating

bit 6

CMIF: Comparator Interrupt Flag bit

= Comparator input has changed (must be cleared in software)

= Comparator input has not changed

bit 5

LVDIF: Low-Voltage Detect Interrupt Flag bit

= The supply voltage has fallen below the specified LVD voltage (must be cleared in software)

= The supply voltage is greater then the specified LVD voltage

bit 4

Unimplemented: Read as ‘0’

bit 3

BCLIF: Bus Collision Interrupt Flag bit

= A bus collision has occurred in the SSP when configured for I2C Master mode

= No bus collision has occurred

bit 2

Unimplemented: Read as ‘0’

bit 1

CCP3IF: CCP3 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 0

CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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